Sounds rather more like a company behind the innovation curve pretending to "skip" the innovation as if to jump into a better innovation.
When the actual truth is they are sticking with the old thing. Reframed as a choice.
If "Ditching 4f" is such a good idea, why show their hand right before their competitors make the foolish choice of releasing it? Why not hold your cards until afterwards?
Unless perhaps this isn't a brilliant strategy but instead a spin for the investors?
Micron is regarded as a very technologically adept. The have a strong track record of delivering leading/performant dram without the manufacturing bells and whistles used by competitors. The CEO was one of the important engineers behind NAND flash back in the day
It's a public company that is beholden to the shareholders. They have to explain what they are doing. But I agree with you, seems sus. Even if you can make more money by scaling the old tech today, that does not justify dropping the future innovation. Especially because by all accounts they are swimming in cash... Unless they are telling the truth and 4f extra complexity does not justify extra cost. I really have no context to evaluate that.
Sounds like innovator's dilemma to me. Their current production lines might be too profitable[0], so diverting expansion capacity to a yet unproven technology (to Micron's to-date profit margin requirements) might be too big of a financial hit. Since they're the ones who came up with 4F design, they must hold a ton of patents on the various incremental improvements. At which point, from a purely cynical and utilitarian view, it would make financial sense to let other players polish the remaining 20% and use patent portfolio as a wedge for mid-term technology transfers.
Or in short: "let others figure out the technical complexities and surrounding economics." - Which would make sense from a company that believes they can catch up once the expensive leg of the manufacturing/scaling research has been completed. Whether that bet is good or not, we'll see.
0: Didn't we read a few days ago here that all of 2027 production capacity has been sold out already?
Given that the stated plan of Micron is to focus on 3D scaling, keeping per-mm^2 production costs low makes perfect sense. When Samsung introduced their first volume V-NAND flash, the 2D feature sizes were larger than leading edge NAND flash because of the tolerances inherent in producing 90 layer flash (aspect ratio matters!) as well as the cost of production equipment. That trend has continued as it is cheaper to produce flash with more layers than to compensate for difficulties arising from decreasing amounts of charge kept in ever smaller cells.
In layperson DRAM-speak this translates to the following: rowhammer attacks are mitigated at the hardware level by increasing the size of and spacing between adjacent cells. At some point further feature size scaling makes it no longer be possible to produce 4F cells that are sufficiently robust against rowhammer type attacks to meet Micron's internal reliability targets. This would be akin to when Intel hit the power wall with the Pentium 4 in the early '00s forcing a change in engineering direction away from merely scaling clock speed.
With Micron's insight into the DRAM order pipeline, management likely has to factor in the chance of oversupply in the next couple of years as significant, which makes the shift in direction even more sensible. DRAM price crashes are a regular occurrence in the industry which lead to anti-dumping tariffs and legal battle in the 1990s (as well as Intel's shift away from DRAM towards complex logic devices in 1985). I'm pretty sure Micron's management is consciously working to avoid a repeat of that protracted legal battle.
I'd rather have an engineering problem over a legal problem any day of the week.
> Which would make sense from a company that believes they can catch up once the expensive leg of the manufacturing/scaling research has been completed. Whether that bet is good or not, we'll see.
The article mentions CXMT has committed to 4F^2 server RDIMMs by end of 2026, and a linked article mentions that CXMT has halved the fab build time from the industry-standard 2 years to just 1. How would Micron catch up with that?
The memory triopoly is in the midst of a slow motion wreck because pumping the brakes will reduce profits; the incumbents are going to have their butts handed to them by CXMT in 2-5 years, and they'll all act like they didn't see it coming as they are bailed-out by the US or SK government, for "National Security."
They really don't. A public company doesn't even have to provide forward-looking earnings guidance, though many choose to do so for strategic reasons. The only reason to make announcements is if there's some strategic benefit to doing so.
Well, yes, but wouldn't this fall under Regulation S-K, Item 303? They don't have to provide forward revenue guidance, but if they're exiting a line of business don't they have to disclose future trends and risks leading to that decision in their 10Q/10K?
> that does not justify dropping the future innovation
Looks like they have mapped the possible paths and consider it a dead end. The density increase is low compared to the effort to process cost, so they just opted for a simpler process with a similar density at a much lower cost per wafer. They might come back to it at some point - they invented it and have substantial IP investment on it.
Also, there might be some cost of opportunity - the AI bubble is now, so anything that diverts from current extremely profitable product lines is a terrible idea. It’s a bubble and they have the fiduciary duty to suck it until it’s dry.
A little hard to explain it to the shareholders. Yeah that expensive investment research project? A total fake out to mislead our competitors. We actually bought snacks and drinks for everyone with that money!
> Sounds rather more like a company behind the innovation curve pretending to "skip" the innovation as if to jump into a better innovation.
This is not unlike the strategy the US employed to win the space race after they were quite behind in said race. It's a bold strategy, Cotton. Let's see if it pays off! (I'm not confident since I don't find the CEO to be anything more than a margin chaser).
At the markups they are making they could be hand-soldering the bits and still be ahead, scaling existing process makes more sense than investing more in research.
> scaling existing process makes more sense than investing more in research.
It doesn't sound like they've stopped investing in research in general. Just one specific area.
"We've been working on this for decades and can't figure out how to commercialize it, so we're going to try different things" is a healthy result, even if other companies got different results.
I hope I am wrong but still dont see any major breakthrough in near future we could bring the BOM cost of DRAM down to below $1/GB. Not even 4F^2 would do that.
Those are completely misleading, because they are not the true cell layouts.
Searching for the Micron patent on 6F^2 cells (US 6,975,531) is much more informative.
The essence of the problem is the following. An ideal memory array cell is formed at the intersection of a vertical line with a horizontal line. A line has the width 2F (i.e. metal width + spacing width), so the area of the cell is 2F * 2F = 4F^2.
Instead of that, most DRAM cells are at the intersection of 2 horizontal lines with 1 vertical line. The single line is a bidirectional data line with the value of the stored bit, while the pair of lines are a write select line and a read select line.
Using separate read and write transistors provides better performance.
The naive layout for a cell where 2 lines intersect with 1 line has an area of 2F * 4F = 8F^2.
An optimized layout where many parts are stacked one over the other and where some lines are shared by adjacent cells, so the spacings are omitted, can have the smaller area of 2F * 3F = 6F^2.
In the 6F^2 cell, there are are 3 transistors, but they have the drain stacked over the source and one transistor is stacked above another, to minimize area.
To make a 4F^2 DRAM cell, there are various approaches, e.g. one could try to stack even more components vertically or one could go back to one-transistor cells, but in modern technology, but it is not obvious whether the much higher processing cost is compensated by the reduced die area.
Micron claims that despite the reduced area the cost would be higher, while the competitors, including the Chinese, claim the opposite.
I don't know any of the details, but dram is basically a whole lot of bits and and each bit is one capacitor and one transistor.
In the diagram for 8F Squared, there's a capacitor at every other junction between word lines and bit lines. If the lines (and inter line spacing) are 2F wide, you have one bit in a 2Fx4F rectangle, or one bit per 8F squared.
In the diagram for 6F Squared, there's a capacitor at every bit line on every other word line. If the lines (and inter line spacing) are 2F wide, you have one bits in each 2Fx3F Rectangle, or one bit per 6F squared. (I guess the word lines without bits are needed for spacing or to drive the transistor or maybe it's just illustration and doesn't mean much)
In the diagram for 4F Squared, there's a transistor at every bit line on every word line. Now you have a bit in every 2Fx2F square, or one bit per 4F Squared.
If you can make dram in all three styles with the same F, 4F squared is twice the density as 8F squared. If the F doesn't hold constant, it's squishier, of course.
Sounds rather more like a company behind the innovation curve pretending to "skip" the innovation as if to jump into a better innovation.
When the actual truth is they are sticking with the old thing. Reframed as a choice.
If "Ditching 4f" is such a good idea, why show their hand right before their competitors make the foolish choice of releasing it? Why not hold your cards until afterwards?
Unless perhaps this isn't a brilliant strategy but instead a spin for the investors?
Micron is regarded as a very technologically adept. The have a strong track record of delivering leading/performant dram without the manufacturing bells and whistles used by competitors. The CEO was one of the important engineers behind NAND flash back in the day
This describes Intel perfectly circa 2010
Every tech giant that fell behind was once regarded as very technologically adept. DEC, Intel, SGI, many of them.
> Why not hold your cards until afterwards?
It's a public company that is beholden to the shareholders. They have to explain what they are doing. But I agree with you, seems sus. Even if you can make more money by scaling the old tech today, that does not justify dropping the future innovation. Especially because by all accounts they are swimming in cash... Unless they are telling the truth and 4f extra complexity does not justify extra cost. I really have no context to evaluate that.
Sounds like innovator's dilemma to me. Their current production lines might be too profitable[0], so diverting expansion capacity to a yet unproven technology (to Micron's to-date profit margin requirements) might be too big of a financial hit. Since they're the ones who came up with 4F design, they must hold a ton of patents on the various incremental improvements. At which point, from a purely cynical and utilitarian view, it would make financial sense to let other players polish the remaining 20% and use patent portfolio as a wedge for mid-term technology transfers.
Or in short: "let others figure out the technical complexities and surrounding economics." - Which would make sense from a company that believes they can catch up once the expensive leg of the manufacturing/scaling research has been completed. Whether that bet is good or not, we'll see.
0: Didn't we read a few days ago here that all of 2027 production capacity has been sold out already?
Given that the stated plan of Micron is to focus on 3D scaling, keeping per-mm^2 production costs low makes perfect sense. When Samsung introduced their first volume V-NAND flash, the 2D feature sizes were larger than leading edge NAND flash because of the tolerances inherent in producing 90 layer flash (aspect ratio matters!) as well as the cost of production equipment. That trend has continued as it is cheaper to produce flash with more layers than to compensate for difficulties arising from decreasing amounts of charge kept in ever smaller cells.
In layperson DRAM-speak this translates to the following: rowhammer attacks are mitigated at the hardware level by increasing the size of and spacing between adjacent cells. At some point further feature size scaling makes it no longer be possible to produce 4F cells that are sufficiently robust against rowhammer type attacks to meet Micron's internal reliability targets. This would be akin to when Intel hit the power wall with the Pentium 4 in the early '00s forcing a change in engineering direction away from merely scaling clock speed.
With Micron's insight into the DRAM order pipeline, management likely has to factor in the chance of oversupply in the next couple of years as significant, which makes the shift in direction even more sensible. DRAM price crashes are a regular occurrence in the industry which lead to anti-dumping tariffs and legal battle in the 1990s (as well as Intel's shift away from DRAM towards complex logic devices in 1985). I'm pretty sure Micron's management is consciously working to avoid a repeat of that protracted legal battle.
I'd rather have an engineering problem over a legal problem any day of the week.
> Which would make sense from a company that believes they can catch up once the expensive leg of the manufacturing/scaling research has been completed. Whether that bet is good or not, we'll see.
The article mentions CXMT has committed to 4F^2 server RDIMMs by end of 2026, and a linked article mentions that CXMT has halved the fab build time from the industry-standard 2 years to just 1. How would Micron catch up with that?
The memory triopoly is in the midst of a slow motion wreck because pumping the brakes will reduce profits; the incumbents are going to have their butts handed to them by CXMT in 2-5 years, and they'll all act like they didn't see it coming as they are bailed-out by the US or SK government, for "National Security."
> They have to explain what they are doing.
They really don't. A public company doesn't even have to provide forward-looking earnings guidance, though many choose to do so for strategic reasons. The only reason to make announcements is if there's some strategic benefit to doing so.
Well, yes, but wouldn't this fall under Regulation S-K, Item 303? They don't have to provide forward revenue guidance, but if they're exiting a line of business don't they have to disclose future trends and risks leading to that decision in their 10Q/10K?
> that does not justify dropping the future innovation
Looks like they have mapped the possible paths and consider it a dead end. The density increase is low compared to the effort to process cost, so they just opted for a simpler process with a similar density at a much lower cost per wafer. They might come back to it at some point - they invented it and have substantial IP investment on it.
Also, there might be some cost of opportunity - the AI bubble is now, so anything that diverts from current extremely profitable product lines is a terrible idea. It’s a bubble and they have the fiduciary duty to suck it until it’s dry.
Wouldn't be the first once hot memory tech that ended up in the scrapheap. See: RDRAM.
why show their hand right before their competitors make the foolish choice of releasing it?
I suspect it is because Micron is a publicly traded company, its management has to answer questions from the investor community.
And because DRAM is a commodity business, profits in the long term are possible even if a company does not win first-to-market profits.
Finally, there is always a market segment that is not betting on the new technology when it is new.
A little hard to explain it to the shareholders. Yeah that expensive investment research project? A total fake out to mislead our competitors. We actually bought snacks and drinks for everyone with that money!
> Sounds rather more like a company behind the innovation curve pretending to "skip" the innovation as if to jump into a better innovation.
This is not unlike the strategy the US employed to win the space race after they were quite behind in said race. It's a bold strategy, Cotton. Let's see if it pays off! (I'm not confident since I don't find the CEO to be anything more than a margin chaser).
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That roadmap image looks like mojibake.
I would say I'm excited to buy 6F²ζÅ DRAM but I assume it's going to be reserved for AI datacentres that don't exist.
There is space in warehouses to store them in the meantime though.
At the markups they are making they could be hand-soldering the bits and still be ahead, scaling existing process makes more sense than investing more in research.
> scaling existing process makes more sense than investing more in research.
It doesn't sound like they've stopped investing in research in general. Just one specific area.
"We've been working on this for decades and can't figure out how to commercialize it, so we're going to try different things" is a healthy result, even if other companies got different results.
I hope I am wrong but still dont see any major breakthrough in near future we could bring the BOM cost of DRAM down to below $1/GB. Not even 4F^2 would do that.
Disappointing that they didn't toss in an image showing the difference between 6T and 4T. Here's a good one:
https://semiwiki.com/forum/threads/samsung-teases-16-layer-3...
That's actually a little confusing to me: The 8F and 6F diagrams don't show why 6F takes less area per cell.
Those are completely misleading, because they are not the true cell layouts.
Searching for the Micron patent on 6F^2 cells (US 6,975,531) is much more informative.
The essence of the problem is the following. An ideal memory array cell is formed at the intersection of a vertical line with a horizontal line. A line has the width 2F (i.e. metal width + spacing width), so the area of the cell is 2F * 2F = 4F^2.
Instead of that, most DRAM cells are at the intersection of 2 horizontal lines with 1 vertical line. The single line is a bidirectional data line with the value of the stored bit, while the pair of lines are a write select line and a read select line.
Using separate read and write transistors provides better performance.
The naive layout for a cell where 2 lines intersect with 1 line has an area of 2F * 4F = 8F^2.
An optimized layout where many parts are stacked one over the other and where some lines are shared by adjacent cells, so the spacings are omitted, can have the smaller area of 2F * 3F = 6F^2.
In the 6F^2 cell, there are are 3 transistors, but they have the drain stacked over the source and one transistor is stacked above another, to minimize area.
To make a 4F^2 DRAM cell, there are various approaches, e.g. one could try to stack even more components vertically or one could go back to one-transistor cells, but in modern technology, but it is not obvious whether the much higher processing cost is compensated by the reduced die area.
Micron claims that despite the reduced area the cost would be higher, while the competitors, including the Chinese, claim the opposite.
Perhaps the cost is higher… for Micron.
[dead]
I don't know any of the details, but dram is basically a whole lot of bits and and each bit is one capacitor and one transistor.
In the diagram for 8F Squared, there's a capacitor at every other junction between word lines and bit lines. If the lines (and inter line spacing) are 2F wide, you have one bit in a 2Fx4F rectangle, or one bit per 8F squared.
In the diagram for 6F Squared, there's a capacitor at every bit line on every other word line. If the lines (and inter line spacing) are 2F wide, you have one bits in each 2Fx3F Rectangle, or one bit per 6F squared. (I guess the word lines without bits are needed for spacing or to drive the transistor or maybe it's just illustration and doesn't mean much)
In the diagram for 4F Squared, there's a transistor at every bit line on every word line. Now you have a bit in every 2Fx2F square, or one bit per 4F Squared.
If you can make dram in all three styles with the same F, 4F squared is twice the density as 8F squared. If the F doesn't hold constant, it's squishier, of course.
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